The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, stricter demands have been placed on lithography process. For example, techniques such as immersion lithography, multiple patterning, extreme ultraviolet (EUV) lithography, and e-beam lithography have been utilized to support critical dimension (CD) requirements of the smaller devices. Such lithography methods, however, may result in truncation error which adversely effects the CD required for the smaller deices. Certain compensation methods, such as increasing the number of pixels in an exposure grid and pre-exposure data preparation/computation, have been used to minimize the truncation error. These compensation methods, however, increase manufacturing time and cost. Accordingly, although existing lithography methods have been generally adequate, they have not been satisfactory in all respects.